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| author | gatecat <gatecat@ds0.me> | 2021-03-17 12:06:09 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-03-17 13:58:04 +0000 |
| commit | dd6d34f461910a120ac95c485fe34cca6485b95e (patch) | |
| tree | 262dd91cfc969b492b99ce8fa7e3c94fd5d412be /kernel | |
| parent | 937392ad337c4f70569535e83f7016245addb2c7 (diff) | |
| download | yosys-dd6d34f461910a120ac95c485fe34cca6485b95e.tar.gz yosys-dd6d34f461910a120ac95c485fe34cca6485b95e.tar.bz2 yosys-dd6d34f461910a120ac95c485fe34cca6485b95e.zip | |
blackbox: Include whiteboxed modules
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 4 | ||||
| -rw-r--r-- | kernel/rtlil.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 32069ce03..87cbaa0d5 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -808,12 +808,12 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const return result; } -std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const +std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const { std::vector<RTLIL::Module*> result; result.reserve(modules_.size()); for (auto &it : modules_) - if (it.second->get_blackbox_attribute()) + if (it.second->get_blackbox_attribute(include_wb)) continue; else if (selected_whole_module(it.first)) result.push_back(it.second); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a747b9d3c..bbdf355fa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1112,7 +1112,7 @@ struct RTLIL::Design std::vector<RTLIL::Module*> selected_modules() const; std::vector<RTLIL::Module*> selected_whole_modules() const; - std::vector<RTLIL::Module*> selected_whole_modules_warn() const; + std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const; #ifdef WITH_PYTHON static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void); #endif |