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| author | Clifford Wolf <clifford@clifford.at> | 2016-12-21 10:16:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-12-21 10:16:47 +0100 |
| commit | f144adec587e2d0e993098abc5b576721ba969dd (patch) | |
| tree | 83ab4b73372913a15505e4482f047547a02ae17f /kernel | |
| parent | f31e6a7174243f463db10afb29f7e2d2b140f56c (diff) | |
| download | yosys-f144adec587e2d0e993098abc5b576721ba969dd.tar.gz yosys-f144adec587e2d0e993098abc5b576721ba969dd.tar.bz2 yosys-f144adec587e2d0e993098abc5b576721ba969dd.zip | |
Added AIGER back-end to automatic back-end detection
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/yosys.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 08fee9741..3d0aca78e 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -903,6 +903,8 @@ void run_backend(std::string filename, std::string command, RTLIL::Design *desig command = "verilog"; else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") command = "ilang"; + else if (filename.size() > 4 && filename.substr(filename.size()-4) == ".aig") + command = "aiger"; else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".blif") command = "blif"; else if (filename.size() > 5 && filename.substr(filename.size()-5) == ".edif") |