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| author | Claire Xen <claire@clairexen.net> | 2021-06-09 13:22:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-09 13:22:52 +0200 |
| commit | 55e8f5061af57bf25bd9e30528de8196c6eabe9e (patch) | |
| tree | e4fcc0a71494dd1023e938b2ed041489c7536014 /manual/APPNOTE_010_Verilog_to_BLIF.tex | |
| parent | 2e697f5655455fd8ce5fec40b94683a11ade24e8 (diff) | |
| parent | 588137cd082849cfa3dee92a01ac4ee91f6ed946 (diff) | |
| download | yosys-55e8f5061af57bf25bd9e30528de8196c6eabe9e.tar.gz yosys-55e8f5061af57bf25bd9e30528de8196c6eabe9e.tar.bz2 yosys-55e8f5061af57bf25bd9e30528de8196c6eabe9e.zip | |
Merge pull request #2817 from YosysHQ/claire/fixemails
Fixing old e-mail addresses and deadnames
Diffstat (limited to 'manual/APPNOTE_010_Verilog_to_BLIF.tex')
| -rw-r--r-- | manual/APPNOTE_010_Verilog_to_BLIF.tex | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 0ecdf6194..16254d593 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -52,7 +52,7 @@ \begin{document} \title{Yosys Application Note 010: \\ Converting Verilog to BLIF} -\author{Clifford Wolf \\ November 2013} +\author{Claire Xenia Wolf \\ November 2013} \maketitle \begin{abstract} @@ -437,12 +437,12 @@ design to fit a certain need without actually touching the RTL code. \begin{thebibliography}{9} \bibitem{yosys} -Clifford Wolf. The Yosys Open SYnthesis Suite. \\ -\url{http://www.clifford.at/yosys/} +Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\ +\url{https://yosyshq.net/yosys/} \bibitem{bigsim} yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\ -\url{https://github.com/cliffordwolf/yosys-bigsim} +\url{https://github.com/YosysHQ/yosys-bigsim} \bibitem{navre} Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\ |