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| author | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
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| committer | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
| commit | bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee (patch) | |
| tree | 1d02541701054a1c3b1cdb66478d0cbc31c2d38f /manual/APPNOTE_010_Verilog_to_BLIF.tex | |
| parent | 8acdd90bc918b780ad45cdac42b3baf84d2cc476 (diff) | |
| parent | 4b4490761949e738dee54bdfc52e080e0a5c9067 (diff) | |
| download | yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.tar.gz yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.tar.bz2 yosys-bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Diffstat (limited to 'manual/APPNOTE_010_Verilog_to_BLIF.tex')
| -rw-r--r-- | manual/APPNOTE_010_Verilog_to_BLIF.tex | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 9ee87bc44..0f521fb0a 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -61,7 +61,7 @@ to easily create complex designs from small HDL code. It is the preferred method of design entry for many designers\footnote{The other half prefers VHDL, a very different but -- of course -- equally powerful language.}. -The Berkeley Logic Interchange Format (BLIF) is a simple file format for +The Berkeley Logic Interchange Format (BLIF) \cite{blif} is a simple file format for exchanging sequential logic between programs. It is easy to generate and easy to parse and is therefore the preferred method of design entry for many authors of logic synthesis tools. @@ -456,6 +456,10 @@ Conor Santifort. Amber ARM-compatible core. \\ Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\ \url{http://www.eecs.berkeley.edu/~alanmi/abc/} +\bibitem{blif} +Berkeley Logic Interchange Format (BLIF) \\ +\url{http://vlsi.colorado.edu/~vis/blif.ps} + \end{thebibliography} |