diff options
| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:33:41 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:33:41 +0200 |
| commit | a734face3a200a6704342e61466ca85fc0c732b0 (patch) | |
| tree | 6a3e2d05816d67d44c972c74e577dd3b14cde305 /manual/APPNOTE_012_Verilog_to_BTOR.tex | |
| parent | 0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47 (diff) | |
| download | yosys-a734face3a200a6704342e61466ca85fc0c732b0.tar.gz yosys-a734face3a200a6704342e61466ca85fc0c732b0.tar.bz2 yosys-a734face3a200a6704342e61466ca85fc0c732b0.zip | |
More deadname stuff
Diffstat (limited to 'manual/APPNOTE_012_Verilog_to_BTOR.tex')
| -rw-r--r-- | manual/APPNOTE_012_Verilog_to_BTOR.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index a96e26503..aabdc63c4 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -52,7 +52,7 @@ \begin{document} \title{Yosys Application Note 012: \\ Converting Verilog to BTOR} -\author{Ahmed Irfan and Clifford Wolf \\ April 2015} +\author{Ahmed Irfan and Claire Xenia Wolf \\ April 2015} \maketitle \begin{abstract} @@ -410,7 +410,7 @@ verification benchmarks with or without memories from Verilog designs. \begin{thebibliography}{9} \bibitem{yosys} -Clifford Wolf. The Yosys Open SYnthesis Suite. \\ +Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\ \url{https://yosyshq.net/yosys/} \bibitem{boolector} |