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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 00:03:00 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-04-01 00:03:00 -0700 |
| commit | f277267916b7b1c97fe90576abecde003cc231ab (patch) | |
| tree | 3e76c4069a6f8fa37e0f53f927738ed2a8665589 /manual/APPNOTE_012_Verilog_to_BTOR.tex | |
| parent | 736a998a75e12ca83b45b74a79e78fae8ab12d16 (diff) | |
| parent | 25533190818b0fe207be9a4626a9a273a08ae219 (diff) | |
| download | yosys-f277267916b7b1c97fe90576abecde003cc231ab.tar.gz yosys-f277267916b7b1c97fe90576abecde003cc231ab.tar.bz2 yosys-f277267916b7b1c97fe90576abecde003cc231ab.zip | |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'manual/APPNOTE_012_Verilog_to_BTOR.tex')
| -rw-r--r-- | manual/APPNOTE_012_Verilog_to_BTOR.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex index 245a6b0b8..1bc277876 100644 --- a/manual/APPNOTE_012_Verilog_to_BTOR.tex +++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex @@ -208,7 +208,7 @@ read_verilog -sv $1; hierarchy -top $3; hierarchy -libdir $DIR; hierarchy -check; proc; opt; -opt_const -mux_undef; opt; +opt_expr -mux_undef; opt; rename -hide;;; splice; opt; memory_dff -wr_only; memory_collect;; @@ -263,7 +263,7 @@ read_verilog -sv $1; hierarchy -top $3; hierarchy -libdir $DIR; hierarchy -check; proc; opt; -opt_const -mux_undef; opt; +opt_expr -mux_undef; opt; rename -hide;;; splice; opt; memory;; |