Merge branch 'master' of https://github.com/cliffordwolf/yosys

1 files changed, 19 insertions, 6 deletions

diff --git a/manual/CHAPTER_Appnotes.tex b/manual/CHAPTER_Appnotes.tex
index 959aabd21..2abfa85da 100644
--- a/manual/CHAPTER_Appnotes.tex
+++ b/manual/CHAPTER_Appnotes.tex
@@ -2,11 +2,24 @@
 \chapter{Application Notes}
 \label{chapter:appnotes}
 
-\begin{fixme}
-This appendix will cover some typical use-cases of Yosys in the form of application notes.
-\end{fixme}
+% \begin{fixme}
+% This appendix will cover some typical use-cases of Yosys in the form of application notes.
+% \end{fixme}
+% 
+% \section{Synthesizing using a Cell Library in Liberty Format}
+% \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
+% \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
 
-\section{Synthesizing using a Cell Library in Liberty Format}
-\section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
-\section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
+This appendix contains copies of the Yosys application notes.
+
+\begin{itemize}
+\item Yosys AppNote 010: Converting Verilog to BLIF \dotfill Page \pageref{app:010} \hskip2cm\null
+\item Yosys AppNote 011: Interactive Design Investigation \dotfill Page \pageref{app:011} \hskip2cm\null
+\end{itemize}
+
+\eject\label{app:010}
+\includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_010_Verilog_to_BLIF.pdf}
+
+\eject\label{app:011}
+\includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_011_Design_Investigation.pdf}