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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-02-08 22:12:29 -0800 |
commit | 0d7e71f7abd49d1c95f0657993b55bb5f66317a1 (patch) | |
tree | b2f77c79c6335d9b2b9dde1938f445c48ba00164 /manual/CHAPTER_CellLib.tex | |
parent | 0c83a30f950d766ddd09bb744ee93e2433095b5c (diff) | |
parent | ef4a28e112be10d3d62395f68e53e8b7e42dbf68 (diff) | |
download | yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.gz yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.tar.bz2 yosys-0d7e71f7abd49d1c95f0657993b55bb5f66317a1.zip |
Merge https://github.com/cliffordwolf/yosys
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
-rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index a831fdf33..7686f5963 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. \end{fixme} \begin{fixme} |