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authorAndrew Zonenberg <azonenberg@drawersteak.com>2017-02-08 22:12:29 -0800
committerAndrew Zonenberg <azonenberg@drawersteak.com>2017-02-08 22:12:29 -0800
commit0d7e71f7abd49d1c95f0657993b55bb5f66317a1 (patch)
treeb2f77c79c6335d9b2b9dde1938f445c48ba00164 /manual/CHAPTER_CellLib.tex
parent0c83a30f950d766ddd09bb744ee93e2433095b5c (diff)
parentef4a28e112be10d3d62395f68e53e8b7e42dbf68 (diff)
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Merge https://github.com/cliffordwolf/yosys
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diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
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--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
using the {\tt abc} pass.
\begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
\end{fixme}
\begin{fixme}