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authorKrystalDelusion <krystinedawn@yosyshq.com>2022-12-08 05:54:08 +1300
committerKrystalDelusion <krystinedawn@yosyshq.com>2022-12-08 05:54:08 +1300
commit1eec255e60f2854b4dd1fa212f02d57eb31c9f19 (patch)
tree9aae278e98bb5f210061c22bcf22d40854d98e8c /manual/CHAPTER_Eval/openmsp430.prj
parent4b95fac13934a39525a934329648cf76e4b4f219 (diff)
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-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v"
-verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v"