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| author | Miodrag Milanović <mmicko@gmail.com> | 2023-01-02 16:07:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-01-02 16:07:36 +0100 |
| commit | 257b41cd1fc3f5ce73fd111e7014150f46af833c (patch) | |
| tree | 33aedbe2ca1f0420b182a7dea8606078044902b4 /manual/CHAPTER_Eval/openmsp430.prj | |
| parent | 3ebc50dee4007f8cca4ffc0e850bc3e86f7641f4 (diff) | |
| parent | f2a4e5f1a077e7980598114adf33951132e60785 (diff) | |
| download | yosys-257b41cd1fc3f5ce73fd111e7014150f46af833c.tar.gz yosys-257b41cd1fc3f5ce73fd111e7014150f46af833c.tar.bz2 yosys-257b41cd1fc3f5ce73fd111e7014150f46af833c.zip | |
Merge pull request #3577 from KrystalDelusion/deprecate_manual
Deprecate manual
Diffstat (limited to 'manual/CHAPTER_Eval/openmsp430.prj')
| -rw-r--r-- | manual/CHAPTER_Eval/openmsp430.prj | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/manual/CHAPTER_Eval/openmsp430.prj b/manual/CHAPTER_Eval/openmsp430.prj deleted file mode 100644 index cb8cd2714..000000000 --- a/manual/CHAPTER_Eval/openmsp430.prj +++ /dev/null @@ -1,14 +0,0 @@ -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_cell.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sync_reset.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_register_file.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg_uart.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_alu.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_watchdog.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_sfr.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_multiplier.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_mem_backbone.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_frontend.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_execution_unit.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_dbg.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/omsp_clock_module.v" -verilog work "../../../../../Work/yosys-tests/openmsp430/rtl/openMSP430.v" |