Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 4 insertions, 4 deletions

diff --git a/manual/CHAPTER_Intro.tex b/manual/CHAPTER_Intro.tex
index 675d24026..f735d46b2 100644
--- a/manual/CHAPTER_Intro.tex
+++ b/manual/CHAPTER_Intro.tex
@@ -45,7 +45,7 @@ researched field. All the information required to write such tools has been open
 available for a long time, and it is therefore likely that a FOSS HDL synthesis tool
 with a feature-complete Verilog or VHDL front end must exist which can be used as a basis for a custom RTL synthesis tool.
 
-Due to the authors preference for Verilog over VHDL it has been decided early
+Due to the author's preference for Verilog over VHDL it was decided early
 on to go for Verilog instead of VHDL\footnote{A quick investigation into FOSS
 VHDL tools yielded similar grim results for FOSS VHDL synthesis tools.}.
 So the existing FOSS Verilog synthesis tools were evaluated (see
@@ -56,12 +56,12 @@ is discussed in this document.
 
 \section{Structure of this Document}
 
-The structure of this document is a follows:
+The structure of this document is as follows:
 
 Chapter~\ref{chapter:intro} is this introduction.
 
 Chapter~\ref{chapter:basics} covers a short introduction to the world of HDL
-synthesis. Basic principles and the terminology is outlined in this chapter.
+synthesis. Basic principles and the terminology are outlined in this chapter.
 
 Chapter~\ref{chapter:approach} gives the quickest possible outline to how the
 problem of implementing a HDL synthesis tool is approached in the case of
@@ -82,7 +82,7 @@ Yosys source code. The chapter concludes with an example loadable module
 for Yosys.
 
 Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} 
-cover three improtant pieces of the synthesis pileline: The Verilog frontend,
+cover three important pieces of the synthesis pipeline: The Verilog frontend,
 the optimization passes and the technology mapping to the target architecture,
 respectively.