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| author | Peter Crozier <peter@crozier.com> | 2020-06-03 17:19:28 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-03 17:19:28 +0100 |
| commit | 0d3f7ea011288e1a1fadd4ae27f1e8a57d729053 (patch) | |
| tree | 07bde0d9f492233728070234aed2abd45fbd464d /manual/CHAPTER_Overview.tex | |
| parent | 17f050d3c6b8934141c42f96a3418de67a687b2c (diff) | |
| parent | 46ed0db2ec883a4ce330c81f321511e36e35c0b3 (diff) | |
| download | yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.tar.gz yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.tar.bz2 yosys-0d3f7ea011288e1a1fadd4ae27f1e8a57d729053.zip | |
Merge branch 'master' into struct
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index be37d8d39..ac0f48e47 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -184,9 +184,12 @@ may hold important information for Yosys developers can be used without disturbing external tools. For example the Verilog backend assigns names in the form {\tt \_{\it integer}\_}. \end{itemize} -In order to avoid programming errors, the RTLIL data structures check if all -identifiers start with either a backslash or a dollar sign and generate a -runtime error if this rule is violated. +Whitespace and control characters (any character with an ASCII code 32 or less) are not allowed +in RTLIL identifiers; most frontends and backends cannot support these characters in identifiers. + +In order to avoid programming errors, the RTLIL data structures check if all identifiers start +with either a backslash or a dollar sign, and contain no whitespace or control characters. +Violating these rules results in a runtime error. All RTLIL identifiers are case sensitive. |