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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 15:58:01 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 15:58:01 -0700 |
| commit | cea7441d8ae7df8d22f510e6a101ec46a9d7751e (patch) | |
| tree | 8067ba09ecfaf6d9cf32e8ed9adba42be27b86a4 /manual/CHAPTER_Overview.tex | |
| parent | c865559f9540c29cb9c6302edc8b4a2620c0b49d (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.tar.gz yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.tar.bz2 yosys-cea7441d8ae7df8d22f510e6a101ec46a9d7751e.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'manual/CHAPTER_Overview.tex')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 1a25c477f..3009bf2c0 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition -(signal and edge-type) and zero or more assignments (RTLIL::SigSig). +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or +more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a |