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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-06 11:46:44 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-06 11:46:44 +0200 |
| commit | 34af6a130370671439da19ef55c2c45a35fd3ad0 (patch) | |
| tree | a822cd8d8cd5aa7f732dcb71fa20e391872e885a /manual/CHAPTER_Prog/stubnets.cc | |
| parent | e1743b3bac8c86f3cf857892dabf66bec5573a7a (diff) | |
| parent | 652345c9cd41a6a93925477e44a6d7925b0d7584 (diff) | |
| download | yosys-34af6a130370671439da19ef55c2c45a35fd3ad0.tar.gz yosys-34af6a130370671439da19ef55c2c45a35fd3ad0.tar.bz2 yosys-34af6a130370671439da19ef55c2c45a35fd3ad0.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'manual/CHAPTER_Prog/stubnets.cc')
| -rw-r--r-- | manual/CHAPTER_Prog/stubnets.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 4d1452c97..ef4b1245d 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -57,7 +57,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // we will record which bits of the (possibly multi-bit) wire are stub signals std::set<int> stub_bits; - // get a signal description for this wire and split it into seperate bits + // get a signal description for this wire and split it into separate bits RTLIL::SigSpec sig = sigmap(wire); // for each bit (unless it is a constant): |