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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-06 08:47:06 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2014-09-06 08:47:06 +0200 |
| commit | 79cbf9067c07ed810b3466174278d77b9a05b46d (patch) | |
| tree | b546123251d39df2ffd115fb0b8a08e57e7cf538 /manual/CHAPTER_Prog | |
| parent | 01ef34c147dd3e3e3d13864f9c726727a4013207 (diff) | |
| download | yosys-79cbf9067c07ed810b3466174278d77b9a05b46d.tar.gz yosys-79cbf9067c07ed810b3466174278d77b9a05b46d.tar.bz2 yosys-79cbf9067c07ed810b3466174278d77b9a05b46d.zip | |
Corrected spelling mistakes found by lintian
Diffstat (limited to 'manual/CHAPTER_Prog')
| -rw-r--r-- | manual/CHAPTER_Prog/stubnets.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 4d1452c97..ef4b1245d 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -57,7 +57,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // we will record which bits of the (possibly multi-bit) wire are stub signals std::set<int> stub_bits; - // get a signal description for this wire and split it into seperate bits + // get a signal description for this wire and split it into separate bits RTLIL::SigSpec sig = sigmap(wire); // for each bit (unless it is a constant): |