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| author | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
| commit | 84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch) | |
| tree | c19a405bc106c2472f1aaa46c36b189db3e5223f /manual/CHAPTER_Prog | |
| parent | 80910d13a610886f4430fbd991ada78b2e586ada (diff) | |
| download | yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.gz yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.bz2 yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.zip | |
Spell check (by Larry Doolittle)
Diffstat (limited to 'manual/CHAPTER_Prog')
| -rw-r--r-- | manual/CHAPTER_Prog/stubnets.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index b2428a671..976107fbf 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -24,7 +24,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // count how many times a single-bit signal is used std::map<RTLIL::SigBit, int> bit_usage_count; - // count ouput lines for this module (needed only for summary output at the end) + // count output lines for this module (needed only for summary output at the end) int line_count = 0; log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name)); |