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authorKrystalDelusion <krystinedawn@yosyshq.com>2022-12-08 05:54:08 +1300
committerKrystalDelusion <krystinedawn@yosyshq.com>2022-12-08 05:54:08 +1300
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diff --git a/manual/CHAPTER_StateOfTheArt/always03.v b/manual/CHAPTER_StateOfTheArt/always03.v
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-module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7,
- out1, out2, out3);
-
-input clock, in1, in2, in3, in4, in5, in6, in7;
-output out1, out2, out3;
-reg out1, out2, out3;
-
-always @(posedge clock) begin
- out1 = in1;
- if (in2)
- out1 = !out1;
- out2 <= out1;
- if (in3)
- out2 <= out2;
- if (in4)
- if (in5)
- out3 <= in6;
- else
- out3 <= in7;
- out1 = out1 ^ out2;
-end
-
-endmodule