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| author | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-12-08 05:54:08 +1300 |
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| committer | KrystalDelusion <krystinedawn@yosyshq.com> | 2022-12-08 05:54:08 +1300 |
| commit | 1eec255e60f2854b4dd1fa212f02d57eb31c9f19 (patch) | |
| tree | 9aae278e98bb5f210061c22bcf22d40854d98e8c /manual/CHAPTER_StateOfTheArt/arrays01.v | |
| parent | 4b95fac13934a39525a934329648cf76e4b4f219 (diff) | |
| download | yosys-1eec255e60f2854b4dd1fa212f02d57eb31c9f19.tar.gz yosys-1eec255e60f2854b4dd1fa212f02d57eb31c9f19.tar.bz2 yosys-1eec255e60f2854b4dd1fa212f02d57eb31c9f19.zip | |
Removing manual files
Diffstat (limited to 'manual/CHAPTER_StateOfTheArt/arrays01.v')
| -rw-r--r-- | manual/CHAPTER_StateOfTheArt/arrays01.v | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/manual/CHAPTER_StateOfTheArt/arrays01.v b/manual/CHAPTER_StateOfTheArt/arrays01.v deleted file mode 100644 index bd0eda294..000000000 --- a/manual/CHAPTER_StateOfTheArt/arrays01.v +++ /dev/null @@ -1,16 +0,0 @@ -module uut_arrays01(clock, we, addr, wr_data, rd_data); - -input clock, we; -input [3:0] addr, wr_data; -output [3:0] rd_data; -reg [3:0] rd_data; - -reg [3:0] memory [15:0]; - -always @(posedge clock) begin - if (we) - memory[addr] <= wr_data; - rd_data <= memory[addr]; -end - -endmodule |