Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 2 insertions, 2 deletions

diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
index a2df8f648..54c076614 100644
--- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
+++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v
@@ -20,12 +20,12 @@
  *  The internal logic cell simulation library.
  *
  *  This verilog library contains simple simulation models for the internal
- *  logic cells (_INV_, _AND_, ...) that are generated by the default technology
+ *  logic cells (_NOT_, _AND_, ...) that are generated by the default technology
  *  mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
  *
  */
 
-module _INV_(A, Y);
+module _NOT_(A, Y);
 input A;
 output Y;
 assign Y = ~A;