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| author | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
| commit | 84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch) | |
| tree | c19a405bc106c2472f1aaa46c36b189db3e5223f /manual/CHAPTER_Techmap.tex | |
| parent | 80910d13a610886f4430fbd991ada78b2e586ada (diff) | |
| download | yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.gz yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.bz2 yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.zip | |
Spell check (by Larry Doolittle)
Diffstat (limited to 'manual/CHAPTER_Techmap.tex')
| -rw-r--r-- | manual/CHAPTER_Techmap.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex index e5c7456c4..13aa8e5a3 100644 --- a/manual/CHAPTER_Techmap.tex +++ b/manual/CHAPTER_Techmap.tex @@ -5,7 +5,7 @@ Previous chapters outlined how HDL code is transformed into an RTL netlist. The RTL netlist is still based on abstract coarse-grain cell types like arbitrary width adders and even multipliers. This chapter covers how an RTL netlist is -transformed into a functionally equivialent netlist utililizing the cell types +transformed into a functionally equivalent netlist utilizing the cell types available in the target architecture. Technology mapping is often performed in two phases. In the first phase RTL cells |