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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 14:34:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 14:34:10 -0700 |
| commit | 213a8955898282163d237944e2eef12e9e0e3e24 (patch) | |
| tree | 43c24650d9659bbf28ef878b236ec081db5dc8da /manual/CHAPTER_Verilog.tex | |
| parent | a8e5d0c402e6218e2a4a03e01f65816e53650b96 (diff) | |
| download | yosys-213a8955898282163d237944e2eef12e9e0e3e24.tar.gz yosys-213a8955898282163d237944e2eef12e9e0e3e24.tar.bz2 yosys-213a8955898282163d237944e2eef12e9e0e3e24.zip | |
opt_expr: optimise $sub when both A[i] and B[i] == 1'b1
Diffstat (limited to 'manual/CHAPTER_Verilog.tex')
0 files changed, 0 insertions, 0 deletions