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| author | Jannis Harder <me@jix.one> | 2023-02-14 17:09:53 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-02-14 17:10:43 +0100 |
| commit | b636af9751993bd35f02f56e68e63a4ef715aa4e (patch) | |
| tree | 210b83acac34fdca8e73e8fb5090804d4e9cb3ed /manual/CHAPTER_Verilog.tex | |
| parent | 5dfad5101d92edb484da2e5306cde58b8d958e7d (diff) | |
| download | yosys-b636af9751993bd35f02f56e68e63a4ef715aa4e.tar.gz yosys-b636af9751993bd35f02f56e68e63a4ef715aa4e.tar.bz2 yosys-b636af9751993bd35f02f56e68e63a4ef715aa4e.zip | |
chformal: Note about using -coverenable with the Verific frontend
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