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| author | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-07-20 15:19:12 +0200 |
| commit | 61ed6b32d1f5fbfda9c6effdaa678092f8156bfa (patch) | |
| tree | 3a53692cbd93a09eabeb67eff5e9e4ace5cf1a3e /manual/FILES_StateOfTheArt/arrays01.v | |
| parent | 3650fd7fbe45a00792770d9ecb9397bc27ea0845 (diff) | |
| download | yosys-61ed6b32d1f5fbfda9c6effdaa678092f8156bfa.tar.gz yosys-61ed6b32d1f5fbfda9c6effdaa678092f8156bfa.tar.bz2 yosys-61ed6b32d1f5fbfda9c6effdaa678092f8156bfa.zip | |
Added Yosys Manual
Diffstat (limited to 'manual/FILES_StateOfTheArt/arrays01.v')
| -rw-r--r-- | manual/FILES_StateOfTheArt/arrays01.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/manual/FILES_StateOfTheArt/arrays01.v b/manual/FILES_StateOfTheArt/arrays01.v new file mode 100644 index 000000000..bd0eda294 --- /dev/null +++ b/manual/FILES_StateOfTheArt/arrays01.v @@ -0,0 +1,16 @@ +module uut_arrays01(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [15:0]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule |