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authorAhmed Irfan <ahmedirfan1983@gmail.com>2014-09-22 11:35:04 +0200
committerAhmed Irfan <ahmedirfan1983@gmail.com>2014-09-22 11:35:04 +0200
commitd3c67ad9b61f602de1100cd264efd227dcacb417 (patch)
tree88c462c53bdab128cd1edbded42483772f82612a /manual/PRESENTATION_ExAdv/Makefile
parentb783dbe148e6d246ebd107c0913de2989ab5af48 (diff)
parent13117bb346dd02d2345f716b4403239aebe3d0e2 (diff)
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc
Diffstat (limited to 'manual/PRESENTATION_ExAdv/Makefile')
-rw-r--r--manual/PRESENTATION_ExAdv/Makefile28
1 files changed, 25 insertions, 3 deletions
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index f38bd6ceb..993a9d9e1 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,6 +1,28 @@
-all: select_01.pdf
+all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
+ macc_simple_xmap.pdf macc_xilinx_xmap.pdf
-select_01.pdf: select_01.v select_01.ys
- ../../yosys select_01.ys
+select.pdf: select.v select.ys
+ ../../yosys select.ys
+
+red_or3x1.pdf: red_or3x1_*
+ ../../yosys red_or3x1_test.ys
+
+sym_mul.pdf: sym_mul_*
+ ../../yosys sym_mul_test.ys
+
+mymul.pdf: mymul_*
+ ../../yosys mymul_test.ys
+
+mulshift.pdf: mulshift_*
+ ../../yosys mulshift_test.ys
+
+addshift.pdf: addshift_*
+ ../../yosys addshift_test.ys
+
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+ ../../yosys macc_simple_test.ys
+
+macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
+ ../../yosys macc_xilinx_test.ys