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author | Clifford Wolf <clifford@clifford.at> | 2014-02-16 17:56:19 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-16 17:56:19 +0100 |
commit | f08c71b96c325f2432abb4f95fd823ae243e003b (patch) | |
tree | ad428898a6d96273014239a63bec4da8af89214d /manual/PRESENTATION_ExAdv/mymul_map.v | |
parent | 42ce3db983fdb512e181daab1817991a661066ff (diff) | |
download | yosys-f08c71b96c325f2432abb4f95fd823ae243e003b.tar.gz yosys-f08c71b96c325f2432abb4f95fd823ae243e003b.tar.bz2 yosys-f08c71b96c325f2432abb4f95fd823ae243e003b.zip |
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Diffstat (limited to 'manual/PRESENTATION_ExAdv/mymul_map.v')
-rw-r--r-- | manual/PRESENTATION_ExAdv/mymul_map.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExAdv/mymul_map.v b/manual/PRESENTATION_ExAdv/mymul_map.v new file mode 100644 index 000000000..e888a7a7c --- /dev/null +++ b/manual/PRESENTATION_ExAdv/mymul_map.v @@ -0,0 +1,15 @@ +module MYMUL(A, B, Y); + parameter WIDTH = 1; + input [WIDTH-1:0] A, B; + output reg [WIDTH-1:0] Y; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + integer i; + always @* begin + Y = 0; + for (i = 0; i < WIDTH; i=i+1) + if (A[i]) + Y = Y + (B << i); + end +endmodule |