Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 3 insertions, 3 deletions

diff --git a/manual/PRESENTATION_ExSyn/techmap_01_map.v b/manual/PRESENTATION_ExSyn/techmap_01_map.v
index 64c0b87c5..4fd86e854 100644
--- a/manual/PRESENTATION_ExSyn/techmap_01_map.v
+++ b/manual/PRESENTATION_ExSyn/techmap_01_map.v
@@ -13,9 +13,9 @@ output [Y_WIDTH-1:0] Y;
 generate
   if ((A_WIDTH == 32) && (B_WIDTH == 32))
     begin
-      wire [15:0] CARRY = |{A[15:0], B[15:0]} && ~|Y[15:0];
-      assign Y[15:0] = A[15:0] + B[15:0];
-      assign Y[31:16] = A[31:16] + B[31:16] + CARRY;
+      wire [16:0] S1 = A[15:0] + B[15:0];
+      wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
+      assign Y = {S2[15:0], S1[15:0]};
     end
   else
     wire _TECHMAP_FAIL_ = 1;