presentation progress

8 files changed, 142 insertions, 0 deletions

diff --git a/manual/PRESENTATION_ExSyn/Makefile b/manual/PRESENTATION_ExSyn/Makefile
index 7c343c4d6..bcff48aad 100644
--- a/manual/PRESENTATION_ExSyn/Makefile
+++ b/manual/PRESENTATION_ExSyn/Makefile
@@ -2,6 +2,8 @@
 TARGETS += proc_01 proc_02 proc_03
 TARGETS += opt_01 opt_02 opt_03 opt_04
 TARGETS += memory_01 memory_02
+TARGETS += techmap_01
+TARGETS += abc_01
 
 all: $(addsuffix .pdf,$(TARGETS))
 
diff --git a/manual/PRESENTATION_ExSyn/abc_01.v b/manual/PRESENTATION_ExSyn/abc_01.v
new file mode 100644
index 000000000..3bc686353
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/abc_01.v
@@ -0,0 +1,10 @@
+module test(input clk, a, b, c,
+            output reg y);
+
+	reg [2:0] q1, q2;
+	always @(posedge clk) begin
+		q1 <= { a, b, c };
+		q2 <= q1;
+		y <= ^q2;
+	end
+endmodule
diff --git a/manual/PRESENTATION_ExSyn/abc_01.ys b/manual/PRESENTATION_ExSyn/abc_01.ys
new file mode 100644
index 000000000..bb0b3780f
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/abc_01.ys
@@ -0,0 +1,5 @@
+read_verilog abc_01.v
+read_verilog -lib abc_01_cells.v
+hierarchy -check -top test
+proc; opt; techmap
+abc -dff -liberty abc_01_cells.lib;;
diff --git a/manual/PRESENTATION_ExSyn/abc_01_cells.lib b/manual/PRESENTATION_ExSyn/abc_01_cells.lib
new file mode 100644
index 000000000..bf6b34788
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/abc_01_cells.lib
@@ -0,0 +1,54 @@
+// test comment
+/* test comment */
+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+  cell(DFFSR) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D;
+                      preset: S;
+                       clear: R; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+    pin(S) { direction: input; }
+    pin(R) { direction: input; }
+  }
+}
diff --git a/manual/PRESENTATION_ExSyn/abc_01_cells.v b/manual/PRESENTATION_ExSyn/abc_01_cells.v
new file mode 100644
index 000000000..444094798
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/abc_01_cells.v
@@ -0,0 +1,40 @@
+
+module BUF(A, Y);
+input A;
+output Y = A;
+endmodule
+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+	Q <= D;
+endmodule
+
+module DFFSR(C, D, Q, S, R);
+input C, D, S, R;
+output reg Q;
+always @(posedge C, posedge S, posedge R)
+	if (S)
+		Q <= 1'b1;
+	else if (R)
+		Q <= 1'b0;
+	else
+		Q <= D;
+endmodule
+
diff --git a/manual/PRESENTATION_ExSyn/techmap_01.v b/manual/PRESENTATION_ExSyn/techmap_01.v
new file mode 100644
index 000000000..c53ca91a8
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/techmap_01.v
@@ -0,0 +1,4 @@
+module test(input [31:0]  a, b,
+            output [31:0] y);
+assign y = a + b;
+endmodule
diff --git a/manual/PRESENTATION_ExSyn/techmap_01.ys b/manual/PRESENTATION_ExSyn/techmap_01.ys
new file mode 100644
index 000000000..8ef9de222
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/techmap_01.ys
@@ -0,0 +1,3 @@
+read_verilog techmap_01.v
+hierarchy -check -top test
+techmap -map techmap_01_map.v;;
diff --git a/manual/PRESENTATION_ExSyn/techmap_01_map.v b/manual/PRESENTATION_ExSyn/techmap_01_map.v
new file mode 100644
index 000000000..64c0b87c5
--- /dev/null
+++ b/manual/PRESENTATION_ExSyn/techmap_01_map.v
@@ -0,0 +1,24 @@
+module \$add (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+generate
+  if ((A_WIDTH == 32) && (B_WIDTH == 32))
+    begin
+      wire [15:0] CARRY = |{A[15:0], B[15:0]} && ~|Y[15:0];
+      assign Y[15:0] = A[15:0] + B[15:0];
+      assign Y[31:16] = A[31:16] + B[31:16] + CARRY;
+    end
+  else
+    wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule