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author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
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committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /manual/PRESENTATION_Intro.tex | |
parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'manual/PRESENTATION_Intro.tex')
-rw-r--r-- | manual/PRESENTATION_Intro.tex | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index af561d01b..1c3b79fa0 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -260,7 +260,7 @@ The following slides cover an example project. This project contains three files \end{itemize} \vfill Direct link to the files: \\ \footnotesize -\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro} +\url{https://github.com/YosysHQ/yosys/tree/master/manual/PRESENTATION_Intro} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -476,7 +476,7 @@ Command reference: \begin{itemize} \item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details. \item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''. -\item Or go to \url{http://www.clifford.at/yosys/documentation.html}. +\item Or go to \url{https://yosyshq.net/yosys/documentation.html}. \end{itemize} \bigskip @@ -806,7 +806,7 @@ but also formal verification, reverse engineering, ...} \begin{itemize} \item Ongoing PhD project on coarse grain synthesis \\ {\setlength{\parindent}{0.5cm}\footnotesize -Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect +Johann Glaser and C. Wolf. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp @@ -913,11 +913,11 @@ control logic because it is simpler than setting up a commercial flow. \begin{frame}{\subsecname} \begin{itemize} \item Website: \\ -\smallskip\hskip1cm\url{http://www.clifford.at/yosys/} +\smallskip\hskip1cm\url{https://yosyshq.net/yosys/} \bigskip \item Manual, Command Reference, Application Notes: \\ -\smallskip\hskip1cm\url{http://www.clifford.at/yosys/documentation.html} +\smallskip\hskip1cm\url{https://yosyshq.net/yosys/documentation.html} \bigskip \item Instead of a mailing list we have a SubReddit: \\ @@ -925,7 +925,7 @@ control logic because it is simpler than setting up a commercial flow. \bigskip \item Direct link to the source code: \\ -\smallskip\hskip1cm\url{https://github.com/cliffordwolf/yosys} +\smallskip\hskip1cm\url{https://github.com/YosysHQ/yosys} \end{itemize} \end{frame} @@ -950,7 +950,7 @@ Questions? \bigskip \bigskip \begin{center} -\url{http://www.clifford.at/yosys/} +\url{https://yosyshq.net/yosys/} \end{center} \end{frame} |