Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 149 insertions, 48 deletions

diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 312cb8986..7697266de 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -5,6 +5,7 @@
 \sectionpage
 \end{frame}
 
+\iffalse
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
 \subsection{Representations of (digital) Circuits}
@@ -51,6 +52,7 @@
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\fi
 
 \subsection{Levels of Abstraction for Digital Circuits}
 
@@ -74,7 +76,7 @@
 \only<6>{Physical Gate Level}%
 \only<7>{Switch Level}}
 \only<1>{
-	Overall view of the circuit: E.g. block-diagrams or instruction-set architecture descriptions
+	Overall view of the circuit. E.g. block-diagrams or instruction-set architecture descriptions.
 }%
 \only<2>{
 	Functional implementation of circuit in high-level programming language (C, C++, SystemC, Matlab, Python, etc.).
@@ -94,7 +96,7 @@
 \only<6>{
 	Netlist of cells that actually are available on the target architecture
 	(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
-	area and/or and/or speed (static timing or number of logic levels).
+	area, power, and/or speed (static timing or number of logic levels).
 }%
 \only<7>{
 	Netlist of individual transistors.
@@ -179,8 +181,8 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 	This scripts contain three types of commands:
 	\begin{itemize}
 	\item {\bf Frontends}, that read input files (usually Verilog).
-	\item {\bf Passes}, that perform transformation on the design in memory.
-	\item {\bf Backends}, that write the design in memory to a file (various formats are available, e.g. Verilog, BLIF, EDIF, SPICE, BTOR, etc.).
+	\item {\bf Passes}, that perform transformations on the design in memory.
+	\item {\bf Backends}, that write the design in memory to a file (various formats are available: Verilog, BLIF, EDIF, SPICE, BTOR, \dots).
 	\end{itemize}
 
 	\bigskip
@@ -247,26 +249,23 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{Example Problem}
+\subsection{Example Project}
 
-\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
-\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
-\end{frame}
-
-\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
-\begin{columns}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
-\column[t]{5cm}
-\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
-\end{columns}
+\begin{frame}[t]{\subsecname}
+The following slides cover an example project. This project contains three files:
+\begin{itemize}
+\item A simple ASIC synthesis script
+\item A digital design written in Verilog
+\item A simple CMOS cell library
+\end{itemize}
+\vfill
+Direct link to the files: \\ \footnotesize
+\url{https://github.com/cliffordwolf/yosys/tree/master/manual/PRESENTATION_Intro}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{Example Synthesis Script}
-
-\begin{frame}[t]{\subsecname}
+\begin{frame}[t]{\subsecname{} -- Synthesis Script}
 
 \setbeamercolor{alerted text}{fg=white,bg=red}
 
@@ -283,9 +282,6 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 \medskip
 {\color{YosysGreen}\# mapping to internal cell library}\\
 \boxalert<9>{techmap}; \boxalert<10>{opt}
-
-\bigskip
-\it continued\dots
 \end{minipage}
 \begin{minipage}[t]{5cm}
 \tt\scriptsize
@@ -326,8 +322,8 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 	Read Verilog source file and convert to internal representation.
 }%
 \only<2>{
-	Elaborate the design hierarchy. Should alsways be the first
-	command after reading the design.
+	Elaborate the design hierarchy. Should always be the first
+	command after reading the design. Can re-run AST front-end.
 }%
 \only<3>{
 	Convert ``processes'' (the internal representation of behavioral
@@ -359,7 +355,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 	Map registers to available hardware flip-flops.
 }%
 \only<12>{
-	Map logix to available hardware gates.
+	Map logic to available hardware gates.
 }%
 \only<13>{
 	Clean up the design (just the last step of {\tt opt}).
@@ -373,6 +369,21 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\begin{frame}[fragile]{\subsecname{} -- Verilog Source: \tt counter.v}
+\lstinputlisting[xleftmargin=1cm, language=Verilog]{PRESENTATION_Intro/counter.v}
+\end{frame}
+
+\begin{frame}[fragile]{\subsecname{} -- Cell Library: \tt mycells.lib}
+\begin{columns}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, lastline=20]{PRESENTATION_Intro/mycells.lib}
+\column[t]{5cm}
+\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=liberty, firstline=21]{PRESENTATION_Intro/mycells.lib}
+\end{columns}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Running the Synthesis Script}
 
 \begin{frame}[t, fragile]{\subsecname{} -- Step 1/4}
@@ -410,8 +421,8 @@ abc -liberty mycells.lib
 clean
 \end{verbatim}
 
-\vfill
-\includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
+\vfill\hfil
+\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf}
 \end{frame}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -422,7 +433,7 @@ clean
 Command reference:
 \begin{itemize}
 \item Use ``{\tt help}'' for a command list and ``{\tt help \it command}'' for details.
-\item Or run ``{\tt yosys -H}'' and ``{\tt yosys -h \it command}''.
+\item Or run ``{\tt yosys -H}'' or ``{\tt yosys -h \it command}''.
 \item Or go to \url{http://www.clifford.at/yosys/documentation.html}.
 \end{itemize}
 
@@ -560,7 +571,7 @@ endmodule
 module cam(clk, wr_enable, wr_addr, wr_data, rd_data, rd_addr, rd_match);
     parameter WIDTH = 8;
     parameter DEPTH = 16;
-    localparam ADDR_BITS = $clog2(DEPTH);
+    localparam ADDR_BITS = $clog2(DEPTH-1);
 
     input clk, wr_enable;
     input [ADDR_BITS-1:0] wr_addr;
@@ -588,6 +599,23 @@ endmodule
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\subsection{Currently unsupported Verilog-2005 language features}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Multi-dimensional arrays (memories)
+\item Writing to arrays using bit- and part-selects (todo for 0.4.0)
+\item The wor/wand wire types (maybe for 0.4.0)
+\item Tri-state logic
+
+\bigskip
+\item Latched logic (is synthesized as logic with feedback loops)
+\item Some non-synthesizable features that should be ignored in synthesis are not supported by the parser and cause a parser error (file a bug report if you encounter this problem)
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Verification of Yosys}
 
 \begin{frame}{\subsecname}
@@ -595,7 +623,7 @@ Contiously checking the correctness of Yosys and making sure that new features
 do not break old ones is a high priority in Yosys.
 
 \bigskip
-There are two external test suites build for Yosys: VlogHammer and yosys-bigsim
+Two external test suites have been built for Yosys: VlogHammer and yosys-bigsim
 (see next slides)
 
 \bigskip
@@ -608,8 +636,8 @@ the internal state after each command.
 
 \begin{frame}[fragile]{\subsecname{} -- VlogHammer}
 VlogHammer is a Verilog regression test suite developed to test the different
-subsystems in Yosys by comparing them to each other and the implementations
-generated by some proprietary tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
+subsystems in Yosys by comparing them to each other and to the output created
+by some other tools (Xilinx Vivado, Xilinx XST, Altera Quartus II, ...).
 
 \bigskip
 Yosys Subsystems tested: Verilog frontend, const folding, const eval, technology mapping,
@@ -624,8 +652,8 @@ assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1}))))}));
 \end{lstlisting}
 
 \bigskip
-Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 20 bugs in
-the proprietary tools used as external reference where found and reported.
+Some bugs in Yosys where found and fixed thanks to VlogHammer. Over 50 bugs in
+the other tools used as external reference where found and reported so far.
 \end{frame}
 
 \begin{frame}{\subsecname{} -- yosys-bigsim}
@@ -634,7 +662,7 @@ benches. yosys-bigsim compares the testbench outpus of simulations of the origin
 Verilog code and synthesis results.
 
 \bigskip
-The following designs are part of yosys-bigsim:
+The following designs are included in yosys-bigsim (excerpt):
 \begin{itemize}
 \item {\tt openmsp430} -- an MSP430 compatible 16 bit CPU
 \item {\tt aes\_5cycle\_2stage} -- an AES encryption core
@@ -651,6 +679,19 @@ The following designs are part of yosys-bigsim:
 
 \subsection{Benefits of Open Source HDL Synthesis}
 
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Cost (also applies to ``free as in free beer'' solutions)
+\item Availablity and Reproducability
+\item Framework- and all-in-one-aspects
+\item Educational Tool
+\end{itemize}
+
+\bigskip
+
+Yosys is open source under the ISC license.
+\end{frame}
+
 \begin{frame}{\subsecname{} -- 1/3}
 \begin{itemize}
 \item Cost (also applies to ``free as in free beer'' solutions): \smallskip\par
@@ -680,7 +721,7 @@ basic functionality. Extensibility was one of Yosys' design goals.
 Because of the framework characterisitcs of Yosys, an increasing number of features
 become available in one tool. Yosys not only can be used for circuit synthesis but
 also for formal equivialence checking, SAT solving, and for circuit analysis, to
-name just a few other application domains. With propritaery software one needs to
+name just a few other application domains. With proprietary software one needs to
 learn a new tool for each of this applications.
 \end{itemize}
 \end{frame}
@@ -688,14 +729,13 @@ learn a new tool for each of this applications.
 \begin{frame}{\subsecname{} -- 3/3}
 \begin{itemize}
 \item Educational Tool: \smallskip\par
-Propritaery synthesis tools are at times where secretive about their inner
-workings. They often are ``black boxes'' where a design goes in and synthesis
-results come out. Yosys is very open about its internals and it is easy to
-observe the different steps of synthesis.
+Propritaery synthesis tools are at times very secretive about their inner
+workings. They often are ``black boxes''. Yosys is very open about its
+internals and it is easy to observe the different steps of synthesis.
 \end{itemize}
 
 \bigskip
-\begin{block}{BTW: Yosys is licensed under the ISC license:}
+\begin{block}{Yosys is licensed under the ISC license:}
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
 copyright notice and this permission notice appear in all copies.
@@ -721,6 +761,67 @@ but also formal verification, reverse engineering, ...}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
+\subsection{Projects (that I know of) using Yosys}
+
+\begin{frame}{\subsecname{} -- (1/2)}
+\begin{itemize}
+\item Ongoing PhD project on coarse grain synthesis \\
+{\setlength{\parindent}{0.5cm}\footnotesize
+Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
+Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
+Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex
+Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp
+201-221. Springer, 2013.}
+
+\bigskip
+\item I know several people that use Yosys simply as Verilog frontend for other
+flows (using either the BLIF and BTOR backends).
+
+\bigskip
+\item I know some analog chip designers that use Yosys for small digital
+control logic because it is simpler than setting up a commercial flow.
+\end{itemize}
+\end{frame}
+
+\begin{frame}{\subsecname{} -- (2/2)}
+\begin{itemize}
+\item Efabless
+\begin{itemize}
+\smallskip \item Not much information on the website (\url{http://efabless.com}) yet.
+\smallskip \item Very cheap 180nm prototyping process (partnering with various fabs)
+\smallskip \item A semiconductor company, NOT an EDA company
+\smallskip \item Web-based design environment
+\smallskip \item HDL Synthesis using Yosys
+\smallskip \item Custom place\&route tool
+
+\bigskip
+\item efabless is building an Open Source IC as reference design. \\
+\hskip1cm (to be announced soon: \url{http://www.openic.io})
+\end{itemize}
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\subsection{Supported Platforms}
+
+\begin{frame}{\subsecname}
+\begin{itemize}
+\item Main development OS: Kubuntu 14.04
+\item There is a PPA for ubuntu (not maintained by me)
+\item Any current Debian-based system should work out of the box
+\item When building on other Linux distributions:
+\begin{itemize}
+\item Needs compiler with some C++11 support
+\item Post to the subreddit if you get stuck
+\end{itemize}
+\item Ported to OS X (Darwin) and OpenBSD
+\item No win32 support (yet)
+\end{itemize}
+\end{frame}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
 \subsection{Other Open Source Tools}
 
 \begin{frame}{\subsecname}
@@ -743,24 +844,24 @@ but also formal verification, reverse engineering, ...}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 
-\subsection{What the Yosys project needs from you}
+\subsection{Yosys needs you}
 
 \begin{frame}{\subsecname}
-We need you as an active user:
+\dots as an active user:
 \begin{itemize}
-\item Use Yosys for on your own designs
+\item Use Yosys for on your own projects
 \item .. even if you are not using it as final synthesis tool
 \item Join the discussion on the Subreddit
 \item Report bugs and send in feature requests
 \end{itemize}
 
 \bigskip
-We need you as a developer:
+\dots as a developer:
 \begin{itemize}
-\item Use Yosys as environment for your research work
+\item Use Yosys as environment for your (research) work
 \item .. you might also want to look into ABC for logic-level stuff
 \item Fork the project on github or create loadable plugins
-\item We desperately need a VHDL frontend or a VHDL-to-Verilog converter
+\item We need a VHDL frontend or a good VHDL-to-Verilog converter
 \end{itemize}
 \end{frame}
 
@@ -794,7 +895,7 @@ We need you as a developer:
 \begin{frame}{\subsecname}
 \begin{itemize}
 \item Yosys is a powerful tool and framework for Verilog synthesis.
-\item Is uses a command-based interface and can be controlled by scripts.
+\item It uses a command-based interface and can be controlled by scripts.
 \item By combining existing commands and implementing new commands Yosys can
 be used in a wide range of application far beyond simple synthesis.
 \end{itemize}