diff options
| author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-09-22 11:35:04 +0200 |
|---|---|---|
| committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-09-22 11:35:04 +0200 |
| commit | d3c67ad9b61f602de1100cd264efd227dcacb417 (patch) | |
| tree | 88c462c53bdab128cd1edbded42483772f82612a /manual/PRESENTATION_Intro | |
| parent | b783dbe148e6d246ebd107c0913de2989ab5af48 (diff) | |
| parent | 13117bb346dd02d2345f716b4403239aebe3d0e2 (diff) | |
| download | yosys-d3c67ad9b61f602de1100cd264efd227dcacb417.tar.gz yosys-d3c67ad9b61f602de1100cd264efd227dcacb417.tar.bz2 yosys-d3c67ad9b61f602de1100cd264efd227dcacb417.zip | |
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation
Conflicts:
backends/btor/btor.cc
Diffstat (limited to 'manual/PRESENTATION_Intro')
| -rw-r--r-- | manual/PRESENTATION_Intro/counter.ys | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys index bcfe387e4..8b3390ed4 100644 --- a/manual/PRESENTATION_Intro/counter.ys +++ b/manual/PRESENTATION_Intro/counter.ys @@ -2,17 +2,18 @@ read_verilog counter.v hierarchy -check -top counter -show -stretch -format pdf -prefix counter_00 +show -notitle -stretch -format pdf -prefix counter_00 # the high-level stuff proc; opt; memory; opt; fsm; opt -show -stretch -format pdf -prefix counter_01 +show -notitle -stretch -format pdf -prefix counter_01 # mapping to internal cell library -techmap; splitnets -ports; opt +techmap; opt -show -stretch -format pdf -prefix counter_02 +splitnets -ports;; +show -notitle -stretch -format pdf -prefix counter_02 # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib @@ -23,4 +24,4 @@ abc -liberty mycells.lib # cleanup clean -show -stretch -lib mycells.v -format pdf -prefix counter_03 +show -notitle -stretch -lib mycells.v -format pdf -prefix counter_03 |