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| author | whitequark <whitequark@whitequark.org> | 2020-08-27 11:24:06 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-27 11:24:06 +0000 |
| commit | 702f7c0253dcf9410050586a5e56da044e3277a3 (patch) | |
| tree | ab94c9121ceb78152a538843e82f69228e938dde /manual/PRESENTATION_Prog.tex | |
| parent | 880df4c89763464b471b1e2044f3f296bb3332b4 (diff) | |
| parent | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (diff) | |
| download | yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.gz yosys-702f7c0253dcf9410050586a5e56da044e3277a3.tar.bz2 yosys-702f7c0253dcf9410050586a5e56da044e3277a3.zip | |
Merge pull request #2358 from whitequark/rename-ilang-to-rtlil
Replace "ILANG" with "RTLIL" everywhere
Diffstat (limited to 'manual/PRESENTATION_Prog.tex')
| -rw-r--r-- | manual/PRESENTATION_Prog.tex | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index a9416f82a..3b61361af 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -22,7 +22,7 @@ \node[data] (rtlil) [below of=astfe, node distance=5em, xshift=7.5em] {RTLIL}; \node[process] (pass) [right of=rtlil, node distance=5em, xshift=7.5em] {Passes}; \node[process] (vlbe) [below of=rtlil, node distance=7em, xshift=-13em] {Verilog Backend}; - \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {ILANG Backend}; + \node[process] (ilangbe) [below of=rtlil, node distance=7em, xshift=0em] {RTLIL Backend}; \node[process, fill=green!5] (otherbe) [below of=rtlil, node distance=7em, xshift=+13em] {Other Backends}; \draw[-latex] (vlog) -- (ast); @@ -105,8 +105,7 @@ For simplicity we only discuss this version of RTLIL in this presentation. \begin{frame}{\subsecname} \begin{itemize} -\item The {\tt dump} command prints the design (or parts of it) in ILANG format. This is -a text representation of RTLIL. +\item The {\tt dump} command prints the design (or parts of it) in the text representation of RTLIL. \bigskip \item The {\tt show} command visualizes how the components in the design are connected. |