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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-06 10:15:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-06 10:15:47 +0200 |
| commit | 652345c9cd41a6a93925477e44a6d7925b0d7584 (patch) | |
| tree | b546123251d39df2ffd115fb0b8a08e57e7cf538 /manual/manual.tex | |
| parent | 01ef34c147dd3e3e3d13864f9c726727a4013207 (diff) | |
| parent | 79cbf9067c07ed810b3466174278d77b9a05b46d (diff) | |
| download | yosys-652345c9cd41a6a93925477e44a6d7925b0d7584.tar.gz yosys-652345c9cd41a6a93925477e44a6d7925b0d7584.tar.bz2 yosys-652345c9cd41a6a93925477e44a6d7925b0d7584.zip | |
Merge pull request #38 from rubund/master
Corrected spelling mistakes found by lintian
Diffstat (limited to 'manual/manual.tex')
| -rw-r--r-- | manual/manual.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/manual.tex b/manual/manual.tex index c305ecb05..19d3b7b2f 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -144,7 +144,7 @@ Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when -testing new synthesis algorithms it might be neccessary to write a custom HDL +testing new synthesis algorithms it might be necessary to write a custom HDL synthesis tool or add new features to an existing one. It this cases the availability of a Free and Open Source (FOSS) synthesis tool that can be used as basis for custom tools would be helpful. |