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| author | Clifford Wolf <clifford@clifford.at> | 2014-04-11 13:06:02 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2014-04-11 13:06:02 +0200 |
| commit | d18c10d991f5563189f26977c60e5b10a93a93b6 (patch) | |
| tree | 133f4fd1b7f4956c53f79fd731c5ebf07c598262 /manual/manual.tex | |
| parent | 6ef2224331e7246d1e107c9e533a7cadce786107 (diff) | |
| parent | 9c1e578afe6af40be4600c20c883fa016fc7fa26 (diff) | |
| download | yosys-d18c10d991f5563189f26977c60e5b10a93a93b6.tar.gz yosys-d18c10d991f5563189f26977c60e5b10a93a93b6.tar.bz2 yosys-d18c10d991f5563189f26977c60e5b10a93a93b6.zip | |
Merge pull request #33 from bentley/dox
Typos and grammar fixes through chapter 2.
Diffstat (limited to 'manual/manual.tex')
| -rw-r--r-- | manual/manual.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/manual.tex b/manual/manual.tex index d6ffd95a6..c305ecb05 100644 --- a/manual/manual.tex +++ b/manual/manual.tex @@ -140,7 +140,7 @@ bookmarksopen=false% \eject \chapter*{Abstract} -Most of todays digital design is done in HDL code (mostly Verilog or VHDL) and +Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and with the help of HDL synthesis tools. In special cases such as synthesis for coarse-grain cell libraries or when @@ -158,7 +158,7 @@ by Yosys to perform advanced gate-level optimizations. An evaluation of Yosys based on real-world designs is included. It is shown that Yosys can be used as-is to synthesize such designs. The results produced by Yosys in this tests where successflly verified using formal verification -and are compareable in quality to the results produced by a commercial +and are comparable in quality to the results produced by a commercial synthesis tool. \bigskip |