Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 19 insertions, 3 deletions

diff --git a/manual/presentation.tex b/manual/presentation.tex
index 35a409cbe..9a876de0c 100644
--- a/manual/presentation.tex
+++ b/manual/presentation.tex
@@ -81,7 +81,7 @@
 
 \title{Yosys Open SYnthesis Suite}
 \author{Clifford Wolf}
-\institute{http://www.clifford.at/}
+\institute{http://www.clifford.at/yosys/}
 
 \usetheme{Madrid}
 \usecolortheme{seagull}
@@ -102,7 +102,7 @@
 \titlepage
 \end{frame}
 
-\setcounter{section}{-2}
+\setcounter{section}{-3}
 
 \section{Abstract}
 \begin{frame}{Abstract}
@@ -122,6 +122,22 @@ non-synthesis applications (such as formal equivialence checking) and
 writing extensions to Yosys using the C++ API.
 \end{frame}
 
+\section{About me}
+\begin{frame}{About me}
+Hi! I'm Clifford Wolf.
+
+\bigskip
+I like writing open source software. For example:
+\begin{itemize}
+\item Yosys
+\item OpenSCAD (now maintained by Marius Kintel)
+\item SPL (a not very popular scripting language)
+\item EmbedVM (a very simple compiler+vm for 8 bit micros)
+\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG, used at LHC)
+\item ROCK Linux (discontinued since 2010)
+\end{itemize}
+\end{frame}
+
 \section{Outline}
 \begin{frame}{Outline}
 Yosys is an Open Source Verilog synthesis tool, and more.
@@ -133,7 +149,7 @@ Outline of this presentation:
 \item Yosys by example: synthesis
 \item Yosys by example: advanced synthesis
 \item Yosys by example: beyond synthesis
-\item Programming Yosys extensions
+\item Writing Yosys extensions in C++
 \end{itemize}
 \end{frame}