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authorEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
committerEddie Hung <eddieh@ece.ubc.ca>2019-03-19 08:52:31 -0700
commit02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch)
treeaf43bf9735fe47b09dbd8807c63fe451eb82aaba /misc/yosys.proto
parent3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff)
parent61f37706f93042c2d1f093dd9bfa717390911eb3 (diff)
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Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'misc/yosys.proto')
-rw-r--r--misc/yosys.proto12
1 files changed, 6 insertions, 6 deletions
diff --git a/misc/yosys.proto b/misc/yosys.proto
index 2870176cb..a583e6265 100644
--- a/misc/yosys.proto
+++ b/misc/yosys.proto
@@ -1,12 +1,12 @@
//
// yosys -- Yosys Open SYnthesis Suite
-//
+//
// Copyright (C) 2018 Serge Bazanski <q3k@symbioticeda.com>
-//
+//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
-//
+//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -73,7 +73,7 @@ message Module {
BitVector bits = 2;
}
map<string, Port> port = 2;
-
+
// Named cells in this module.
message Cell {
// Set to true when the name of this cell is automatically created and
@@ -129,7 +129,7 @@ message Model {
TYPE_FALSE = 6;
};
Type type = 1;
-
+
message Port {
// Name of port.
string portname = 1;
@@ -148,7 +148,7 @@ message Model {
// Set for AND, NAND.
Gate gate = 3;
}
-
+
// Set when the node drives given output port(s).
message OutPort {
// Name of port.