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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/abc/blifparse.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/abc/blifparse.cc')
| -rw-r--r-- | passes/abc/blifparse.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 1d4da19ad..65ebe541d 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -177,10 +177,10 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) } input_sig.append(wire); } - output_sig = input_sig.extract(input_sig.width-1, 1); - input_sig = input_sig.extract(0, input_sig.width-1); + output_sig = input_sig.extract(input_sig.__width-1, 1); + input_sig = input_sig.extract(0, input_sig.__width-1); - if (input_sig.width == 0) { + if (input_sig.__width == 0) { RTLIL::State state = RTLIL::State::Sa; while (1) { if (!read_next_line(buffer, buffer_size, line_count, f)) @@ -218,8 +218,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) RTLIL::Cell *cell = new RTLIL::Cell; cell->name = NEW_ID; cell->type = "$lut"; - cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.width); - cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.width); + cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.__width); + cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.__width); cell->connections["\\I"] = input_sig; cell->connections["\\O"] = output_sig; lutptr = &cell->parameters.at("\\LUT"); |