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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
| commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/add.cc | |
| parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
| parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
| download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip | |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index ce8ecc32d..1401193fd 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections_.count(name) > 0) + if (it.second->connections().count(name) > 0) continue; - it.second->connections_[name] = wire; + it.second->set(name, wire); log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str()); } } |