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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:42:12 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:45:47 +0200 |
| commit | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (patch) | |
| tree | 016692552e9880b3e37a715b53f45db707c83a91 /passes/cmds/add.cc | |
| parent | ea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 (diff) | |
| download | yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.gz yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.bz2 yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.zip | |
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index cfccca966..af6f7043d 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -71,7 +71,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; if (it.second->hasPort(name)) continue; |