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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:42:12 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-18 17:45:47 +0200 |
| commit | f4abc21d8ad79621cc24852bd76abf40a9d9f702 (patch) | |
| tree | 016692552e9880b3e37a715b53f45db707c83a91 /passes/cmds/bugpoint.cc | |
| parent | ea8ac0aaad3a1f89ead8eb44b2fef5927f29a099 (diff) | |
| download | yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.gz yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.tar.bz2 yosys-f4abc21d8ad79621cc24852bd76abf40a9d9f702.zip | |
Add "whitebox" attribute, add "read_verilog -wb"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'passes/cmds/bugpoint.cc')
| -rw-r--r-- | passes/cmds/bugpoint.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 606276e64..4b22f6d2d 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -128,7 +128,7 @@ struct BugpointPass : public Pass { { for (auto &it : design_copy->modules_) { - if (it.second->get_bool_attribute("\\blackbox")) + if (it.second->get_blackbox_attribute()) continue; if (index++ == seed) @@ -143,7 +143,7 @@ struct BugpointPass : public Pass { { for (auto mod : design_copy->modules()) { - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; for (auto wire : mod->wires()) @@ -168,7 +168,7 @@ struct BugpointPass : public Pass { { for (auto mod : design_copy->modules()) { - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; for (auto &it : mod->cells_) @@ -186,7 +186,7 @@ struct BugpointPass : public Pass { { for (auto mod : design_copy->modules()) { - if (mod->get_bool_attribute("\\blackbox")) + if (mod->get_blackbox_attribute()) continue; for (auto cell : mod->cells()) |