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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 00:21:46 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-08 20:16:29 +0100 |
| commit | 4e03865d5bf3fafe0bd3735c88431675d53d2663 (patch) | |
| tree | 7ef637bd0526b498d32386bc1c79c671a02af7f0 /passes/cmds/check.cc | |
| parent | c00a29296c8d3446c7cfe253080c7e33358219b0 (diff) | |
| download | yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.tar.gz yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.tar.bz2 yosys-4e03865d5bf3fafe0bd3735c88431675d53d2663.zip | |
Add support for memory writes in processes.
Diffstat (limited to 'passes/cmds/check.cc')
| -rw-r--r-- | passes/cmds/check.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 36febb98a..b502b0788 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -141,6 +141,14 @@ struct CheckPass : public Pass { for (auto bit : sigmap(action.second)) if (bit.wire) used_wires.insert(bit); } + for (auto memwr : sync->mem_write_actions) { + for (auto bit : sigmap(memwr.address)) + if (bit.wire) used_wires.insert(bit); + for (auto bit : sigmap(memwr.data)) + if (bit.wire) used_wires.insert(bit); + for (auto bit : sigmap(memwr.enable)) + if (bit.wire) used_wires.insert(bit); + } } } |