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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-13 14:40:49 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-13 14:40:49 +0100 |
| commit | a0a0594d1e9d0699a6875a9899752de9dd5d261d (patch) | |
| tree | 1fa370fed3afbf80259f11dd7c83ced22819232b /passes/cmds/check.cc | |
| parent | 04cb947d6a35b3773e694651971f28cbf83952e9 (diff) | |
| download | yosys-a0a0594d1e9d0699a6875a9899752de9dd5d261d.tar.gz yosys-a0a0594d1e9d0699a6875a9899752de9dd5d261d.tar.bz2 yosys-a0a0594d1e9d0699a6875a9899752de9dd5d261d.zip | |
hotfix in "check" command
Diffstat (limited to 'passes/cmds/check.cc')
| -rw-r--r-- | passes/cmds/check.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 39a732fff..6840572eb 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -91,7 +91,8 @@ struct CheckPass : public Pass { wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i)); } if (wire->port_output) - for (auto bit : sigmap(wire)) used_wires.insert(bit); + for (auto bit : sigmap(wire)) + if (bit.wire) used_wires.insert(bit); } for (auto it : wire_drivers) |