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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 16:38:54 +0200 |
| commit | cdae8abe16847c533171fed111beea7b52202cce (patch) | |
| tree | bf8dddb4a4ca4d70c83603ef61b2d22cb95d153a /passes/cmds/connect.cc | |
| parent | b5a9e51b966abdfedc9309defa79b5141928e84a (diff) | |
| download | yosys-cdae8abe16847c533171fed111beea7b52202cce.tar.gz yosys-cdae8abe16847c533171fed111beea7b52202cce.tar.bz2 yosys-cdae8abe16847c533171fed111beea7b52202cce.zip | |
Renamed port access function on RTLIL::Cell, added param access functions
Diffstat (limited to 'passes/cmds/connect.cc')
| -rw-r--r-- | passes/cmds/connect.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 3e13fd4d4..30c80f732 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -176,7 +176,7 @@ struct ConnectPass : public Pass { if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); + module->cells_.at(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); |