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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 10:18:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 11:18:30 +0200 |
| commit | 10e5791c5e5660cb784503d36439ee90d61eb06b (patch) | |
| tree | d7bd3d8f1d0254e14fcf68ce25545f42afab9724 /passes/cmds/copy.cc | |
| parent | d088854b47f5f77c6a62be2ba4b895164938d7a2 (diff) | |
| download | yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.gz yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.tar.bz2 yosys-10e5791c5e5660cb784503d36439ee90d61eb06b.zip | |
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'passes/cmds/copy.cc')
| -rw-r--r-- | passes/cmds/copy.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index 4b1a8db81..fc801f61f 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -41,14 +41,14 @@ struct CopyPass : public Pass { std::string src_name = RTLIL::escape_id(args[1]); std::string trg_name = RTLIL::escape_id(args[2]); - if (design->modules.count(src_name) == 0) + if (design->modules_.count(src_name) == 0) log_cmd_error("Can't find source module %s.\n", src_name.c_str()); - if (design->modules.count(trg_name) != 0) + if (design->modules_.count(trg_name) != 0) log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); - design->modules[trg_name] = design->modules.at(src_name)->clone(); - design->modules[trg_name]->name = trg_name; + design->modules_[trg_name] = design->modules_.at(src_name)->clone(); + design->modules_[trg_name]->name = trg_name; } } CopyPass; |