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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2023-01-17 12:58:08 +0100 |
| commit | 6574553189fb6ccb5d00a0c043671a625672b3d3 (patch) | |
| tree | 57e3212ee75493d9f4939c9f9029b95880367a76 /passes/cmds/design.cc | |
| parent | 956c4e485a9463863f60c4dd03372db3fa8332a4 (diff) | |
| download | yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.gz yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.tar.bz2 yosys-6574553189fb6ccb5d00a0c043671a625672b3d3.zip | |
Fixes for some of clang scan-build detected issues
Diffstat (limited to 'passes/cmds/design.cc')
| -rw-r--r-- | passes/cmds/design.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 169f7cc4a..168d38563 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -118,6 +118,9 @@ struct DesignPass : public Pass { std::string save_name, load_name, as_name, delete_name; std::vector<RTLIL::Module*> copy_src_modules; + if (!design) + log_cmd_error("No default design.\n"); + size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -280,7 +283,7 @@ struct DesignPass : public Pass { done[mod->name] = prefix; } - while (!queue.empty()) + while (!queue.empty() && copy_from_design) { pool<Module*> old_queue; old_queue.swap(queue); |