diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-08-14 10:56:05 +0200 |
| commit | 84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch) | |
| tree | c19a405bc106c2472f1aaa46c36b189db3e5223f /passes/cmds/design.cc | |
| parent | 80910d13a610886f4430fbd991ada78b2e586ada (diff) | |
| download | yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.gz yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.tar.bz2 yosys-84bf862f7c58c2b69babf043ff5032f924a3ee4d.zip | |
Spell check (by Larry Doolittle)
Diffstat (limited to 'passes/cmds/design.cc')
| -rw-r--r-- | passes/cmds/design.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 16a4e64ae..e900e7b9c 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -80,7 +80,7 @@ struct DesignPass : public Pass { log("\n"); log(" design -copy-to <name> [-as <new_mod_name>] [selection]\n"); log("\n"); - log("Copy modules from the current design into the soecified one.\n"); + log("Copy modules from the current design into the specified one.\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) |