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authorClifford Wolf <clifford@clifford.at>2014-07-26 16:00:30 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 16:00:30 +0200
commita84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch)
treee4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/scatter.cc
parentcd6574ecf652901573cbc6b89e1a59dd383ec496 (diff)
parentf8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff)
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Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/cmds/scatter.cc')
-rw-r--r--passes/cmds/scatter.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index 0028f7ead..35ce0a110 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -58,10 +58,10 @@ struct ScatterPass : public Pass {
if (ct.cell_output(c.second->type, p.first)) {
RTLIL::SigSig sigsig(p.second, wire);
- mod_it.second->connections_.push_back(sigsig);
+ mod_it.second->connect(sigsig);
} else {
RTLIL::SigSig sigsig(wire, p.second);
- mod_it.second->connections_.push_back(sigsig);
+ mod_it.second->connect(sigsig);
}
p.second = wire;