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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
| commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
| tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/scc.cc | |
| parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
| parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
| download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip | |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/cmds/scc.cc')
| -rw-r--r-- | passes/cmds/scc.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 40a2e48cb..3380a935a 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -132,7 +132,7 @@ struct SccWorker RTLIL::SigSpec inputSignals, outputSignals; - for (auto &conn : cell->connections_) + for (auto &conn : cell->connections()) { bool isInput = true, isOutput = true; |