diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-07-22 19:56:17 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-22 20:39:37 +0200 |
| commit | a233762a815fc180b371f699e865a7d7aed77bca (patch) | |
| tree | 722e54921bbc09595c046c6045cd531445945fc9 /passes/cmds/select.cc | |
| parent | 3b5f4ff39c94a5a664043f35b95a50240ffe9d12 (diff) | |
| download | yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.gz yosys-a233762a815fc180b371f699e865a7d7aed77bca.tar.bz2 yosys-a233762a815fc180b371f699e865a7d7aed77bca.zip | |
SigSpec refactoring: renamed chunks and width to __chunks and __width
Diffstat (limited to 'passes/cmds/select.cc')
| -rw-r--r-- | passes/cmds/select.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 9ef60a28f..068162eb1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -415,7 +415,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v include_match: is_input = mode == 'x' || ct.cell_input(cell.second->type, conn.first); is_output = mode == 'x' || ct.cell_output(cell.second->type, conn.first); - for (auto &chunk : conn.second.chunks) + for (auto &chunk : conn.second.__chunks) if (chunk.wire != NULL) { if (max_objects != 0 && selected_wires.count(chunk.wire) > 0 && lhs.selected_members[mod->name].count(cell.first) == 0) if (mode == 'x' || (mode == 'i' && is_output) || (mode == 'o' && is_input)) |