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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-19 08:52:31 -0700 |
| commit | 02e8dc7ad2e13a43a310d311302c6db8168e6c11 (patch) | |
| tree | af43bf9735fe47b09dbd8807c63fe451eb82aaba /passes/cmds/setundef.cc | |
| parent | 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a (diff) | |
| parent | 61f37706f93042c2d1f093dd9bfa717390911eb3 (diff) | |
| download | yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.gz yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.tar.bz2 yosys-02e8dc7ad2e13a43a310d311302c6db8168e6c11.zip | |
Merge https://github.com/YosysHQ/yosys into read_aiger
Diffstat (limited to 'passes/cmds/setundef.cc')
| -rw-r--r-- | passes/cmds/setundef.cc | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 56ef2d125..f6949c820 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -143,6 +143,9 @@ struct SetundefPass : public Pass { log(" -init\n"); log(" also create/update init values for flip-flops\n"); log("\n"); + log(" -params\n"); + log(" replace undef in cell parameters\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -150,6 +153,7 @@ struct SetundefPass : public Pass { bool undriven_mode = false; bool expose_mode = false; bool init_mode = false; + bool params_mode = false; SetundefWorker worker; log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n"); @@ -199,6 +203,10 @@ struct SetundefPass : public Pass { init_mode = true; continue; } + if (args[argidx] == "-params") { + params_mode = true; + continue; + } if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { got_value = true; worker.next_bit_mode = MODE_RANDOM; @@ -228,6 +236,18 @@ struct SetundefPass : public Pass { for (auto module : design->selected_modules()) { + if (params_mode) + { + for (auto *cell : module->selected_cells()) { + for (auto ¶meter : cell->parameters) { + for (auto &bit : parameter.second.bits) { + if (bit > RTLIL::State::S1) + bit = worker.next_bit(); + } + } + } + } + if (undriven_mode) { if (!module->processes.empty()) |