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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 16:00:30 +0200 |
commit | a84cb0493566f8f5eb610c6d7b67dda85b0f227b (patch) | |
tree | e4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /passes/cmds/setundef.cc | |
parent | cd6574ecf652901573cbc6b89e1a59dd383ec496 (diff) | |
parent | f8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (diff) | |
download | yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.gz yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.tar.bz2 yosys-a84cb0493566f8f5eb610c6d7b67dda85b0f227b.zip |
Merge automatic and manual code changes for new cell connections API
Diffstat (limited to 'passes/cmds/setundef.cc')
-rw-r--r-- | passes/cmds/setundef.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e1005a270..e26106103 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -135,7 +135,7 @@ struct SetundefPass : public Pass { CellTypes ct(design); for (auto &it : module->cells) - for (auto &conn : it.second->connections_) + for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_signals.del(sigmap(conn.second)); @@ -144,7 +144,7 @@ struct SetundefPass : public Pass { RTLIL::SigSpec bits; for (int i = 0; i < c.width; i++) bits.append(worker.next_bit()); - module->connections_.push_back(RTLIL::SigSig(c, bits)); + module->connect(RTLIL::SigSig(c, bits)); } } |